Translation Lookaside Buffer in Operating System

The processes are executed by the CPU and this execution is done in the RAM and so the processor needs to find the required page of the process in the main memory. Now, we know that the CPU generates a Logical Address and we use that to get the frame number from the Page Table so that we can use this Frame number to find the page in the Main Memory.

Now, the problem here is that the Page Table is stored in the main memory too, and we must know that to access anything in from the main memory we require a time that is known Main Memory Access Time, and suppose this Time is x, then we would require 2x time for getting the page to execute, first we will have to search for the Page Table and then the Page in the main memory using the Frame Number. 

We want to do something better than this time complexity, why we cannot use registers??

Yes, registers are high-speed memory locations so, we should store page tables in them and access the Frame Numbers from it only? right? But no. Registers are fast, but they have limited memory and they can store generally 0.9 to 1k page entries and suppose we have 1M page entries then this idea is not practical. 

So, we use the Translation Lookaside Buffer for storing the Page Tables, so that we don't have to access the Main Memory twice and to get optimal speed. TLB is nothing but a special cache used to store recently used transactions. TLB contains page table entries that have been recently used. We basically use TLB to find the Frame Number using the Logical Address generated by the CPU faster. But it is not guaranteed that we will get the Page Number in the TLB so, it is like a hit and try method. We will try to find the Page in the TLB and if we find the Page then this is a "Hit" condition, and we will just generate the Physical Address and then at last will find the Page in the Main Memory in the Main Memory Access Time. 

In the case, when we couldn't find the page in the TLB we will have to again switch to the Page Table in the main memory to generate the Physical Address, and this condition is known as a "Miss" Condition. And in this condition you can see that we first searched in the TLB then it was a miss so we again got back to the Page Table in the Main Memory and lastly searched for the Page in the Main Memory. So, if the Main Memory Access Time is suppose x, and the TLB access time is suppose y. We spent y+x+x time to get the page to execute. But in the Hit Condition we just had y+x. 

So, this is what will be helpful for you guys in the numericals of  TLB, knowing the time requirements in both the conditions( Hit and Miss ).

Mostly, in numericals you will be asked to find the Effective Memory Access Time(EMAT).

EMAT=HitProbability*(y+x) + MissProbability(y+x+x)

where, y=TLB Access Time,

                x=Main Memory Access Time